A conventional fabricating method of a transistor comprises forming shallow trench isolation (STI) structures and filling the STI structures. The method may also include performing a chemical mechanical polishing (CMP) process, forming a gate electrode, and depositing an interlayer insulation layer.
For example, U.S. Pat. No. 6,281,082 to Chen et al. discloses a method of forming metal oxide semiconductor (MOS) transistors with a common shallow trench isolation and interlevel dielectric gap fill. The Chen et al. patent forms trenches and, then, forming gate electrodes. Here, spacers are formed in the trenches to fill easily the trenches.
FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a convention fabricating method. STIs are formed in a semiconductor substrate 1 through an etching process and filled with oxide. A CMP process is performed to form trench-type device isolation layers 3. Next, a gate oxide layer 5 and a gate polysilicon layer 7 are formed on the semiconductor substrate 1 including the device isolation layers 3. An ion implantation process 9 for the formation of a lightly doped drain (LDD) is performed using the gate polysilicon layer 7 as a mask. A tetraethyl orthosilicate (TEOS) //SiN/TEOS layer is formed over the resulting substrate 1. Spacers 11 are formed through an etching process for the TEOS/SiN/TEOS layer. Next, an ion implantation process 13 for the formation of junction region is performed using the spacers 11 as a mask. Finally, an insulating layer 15 is deposited over the resulting substrate 1 and etched to form metal contact holes 17.
However, such a conventional method includes a first planarization process after the deposition of a gap filling oxide layer in trenches and a second planarization process after the deposition of an interlayer insulation layer and, therefore complicates the fabricating process. In addition, a pad nitride layer and a pad oxide layer have to be necessarily formed in the conventional method. However, when a CMP process is applied to the substrate including the pad nitride layer and the pad oxide layer, a residual nitride layer may be generated and the pad oxide layer may be damaged. The residual nitride layer and the damage of pad oxide layer may deteriorate circuit performance and reduce a device yield as the pitch between metals is reduced more and more due to high-integration. Moreover, the conventional method increases manufacturing costs due to complex fabricating steps.